In modern multiprocessor (MP)-socket computer systems, various topologies are possible. Such systems often include many different semiconductor components realized as integrated circuits (ICs). The ICs include processors, memories, chipsets, input/output hubs (IOHs) and so forth.
As process nodes advance, greater amounts of functionality can be incorporated into a single semiconductor die. One integration trend is to integrate an IO component such as functionality of an IOH into a central processing unit (CPU) die. The main motivation for doing so is to reduce the bill of material (BOM) cost of a computer system, and enable small form factors while reducing overall power consumption.
But problems arise once an IO component is integrated on the same chip with a multiprocessor. Traditional IO integration treats the IO component as a separate caching agent, meaning that dedicated logic is associated with the IO component to handle cache coherency operations. When an IO agent is performing read/write operations to main memory, it has to snoop the CPU side cache to maintain cache coherency. In MP systems, this becomes a major scaling problem. For example, in an 8 socket system, there are effectively 16 caching agents in the system, which can degrade performance. And the efforts to scale up a system to support these many caching agents are not trivial.